The 68030 Mk I is intended as a relatively modest Unix machine. It sports the following features: * 68030 CPU + 68882 FPU running at 25MHz. * Up to 256MB of 60ns dynamic RAM (as 2x 128MB 72-pin SIMMs). * 4MB of 10ns static RAM. * 1MB of flash ROM containing system firmware. * 2 16550-compatible serial ports (provided by a TL16C2552). * An ATA disk interface supporting 1 or 2 drives. * A 10Mb/s twisted pair Ethernet interface (provided by an RTL8019AS). * An I2C interface (provided by a PCF8584) and real-time clock/calendar with battery backup (provided by a DS3231). * A system timer. * An expansion port with limited bus master capability. * An interrupt controller that supports 6 open-drain level-triggered interrupt inputs with a global interrupt enable/disable control, plus a non-maskable interrupt. * An ATX power supply with a microcontroller that provides software- controlled power-off and system reset. The system is built around 3 ATF1508AS CPLDs: SYSCTL (system controller), DRAMCTL (DRAM controller), and ISACTL (ISA bus cycle controller). All timing is derived from a 50MHz crystal oscillator that directly clocks the DRAM controller and is divided down by other controllers to provide the CPU (and bus) clock, the I2C clock, and the system timer base clock. The system makes extensive use of the 68030's dynamic bus sizing mechanism. This allows the peripheral address space to be densely- packed and for 16-bit little-endian peripherals (such as ATA disks and the Ethernet interface) to be handled rationally: